Fourth International Workshop on
High-level Parallel Programming and Applications (HLPP 2010)
Baltimore, Maryland, September 25, 2010
Affiliated to ICFP 2010
Sponsored by ACM SIGPLAN

Aims and Scope

As processor and system manufacturers adjust their roadmaps towards increasing levels of both inter and intra-chip parallelism, so the urgency of reorienting the mainstream software industry towards these architectures grows.

At present, popular parallel and distributed programming methodologies are dominated by low-level techniques such as send/receive message passing, or equivalently unstructured shared memory mechanisms.

Higher-level, structured approaches offer many possible advantages and have a key role to play in the scalable exploitation of ubiquitous parallelism.

This workshop provides a forum for discussion and research about such high-level approaches to parallel programming.

Workshop Program

• 08:00-08:45: Continental Breakfast
• 09:00-10:00: Invited Talk
  • Zhenjiang Hu (National Institute of Informatics)
    Calculational Parallel Programming
    [slides]
• 10:00-10:30: Break
• 10:30-12:00: Session "Skeletal Parallelism"
  • Johan Enmyren and Christoph Kessler
    SkePU: A Multi-Backend Skeleton Programming Library for Multi-GPU Systems
    [slides]
  • Kiminori Matsuzaki and Kento Emoto
    Lessons from Implementing the BiCGStab Method with SkeTo Library
    [slides]
  • Oleg Lobachev and Rita Loogen
    Estimating Parallel Performance, A Skeleton-Based Approach
    [slides]
• 12:00-12:30: Session "Verification of High-Level Parallel Programs"
  • Frédéric Gava and Jean Fortin
    BSP-Why: an intermediate language for deductive verification of BSP programs
    [slides]
• 12:30-02:00: Lunch
• 02:00-03:00: Invited Talk
  • Phil Trinder (Heriot-Watt University)
    SymGrid-Par: A Standard Skeleton-Based Framework for Computational Algebra Systems
    [slides]
• 03:00-03:30: Break
• 03:30-04:30: Session "Bulk Synchronous Parallelism"
  • Md. Mostofa Ali Patwary, Rob H. Bisseling and Fredrik Manne
    Parallel Greedy Graph Matching using an Edge Partitioning Approach
    [slides]
  • Joel Falcou, Khaled Hamidouche and Daniel Etiemble
    Hybrid Bulk Synchronous Parallelism Library for Clustered SMP Architectures
    [slides]
• 04:30-05:00: Break

Topics

We welcomed submission of original, unpublished papers in English on topics including (but not limited to) the following aspects of multi-core, parallel, distributed, grid and cloud computing:

• High-level programming and performance models (BSP, CGM, LogP, MPM, etc.) and tools
• Declarative parallel programming methodologies
• Algorithmic skeletons and constructive methods
• Declarative parallel programming languages and libraries: semantics and implementation
• Verification of declarative parallel and distributed programs
• Applications using high-level languages and tools
• Teaching experience with high-level tools and methods

Programme Committee

• Anne Benoit (ENS Lyon, France)
• Murray Cole (University of Edinburgh, UK)
• Alexandros Gerbessiotis (New Jersey Institute of Technology, USA)
• Christoph Kessler (Linköpings Universitet, Sweden)
• Herbert Kuchen (University of Muenster, Germany)
• Rita Loogen (University of Marburg, Germany)
• Frédéric Loulergue (University of Orléans, France), chair
• Kiminori Matsuzaki (Kochi University of Technology, Japan)
• Samuel Midkiff (Purdue University, USA)
• Susanna Pelagatti (University of Pisa, Italy)
• Sukyoung Ryu (Korea Advanced Institute of Science and Technology, Korea)
• Kazunori Ueda (Waseda University, Japan)

Important Dates

• Submission (extended) : 14 June 2010, 11:59 AM GMT
• Notification: 14 July 210
• Final version: 30 July 2010

Submission

Papers must be submitted online via EasyChair.

Submitted papers should be in portable document format (PDF), formatted using the ACM SIGPLAN style guidelines. The text should be in a 9pt font in two columns; the length is restricted to 10 pages.

Papers must report previously unpublished work and not be submitted concurrently to another conference with refereed proceedings. Accepted papers must be presented at the workshop by one of the authors. Accepted papers will be published by the ACM and will appear in the ACM Digital Library.

Organizer

Frédéric Loulergue
Laboratoire d'Informatique Fondamentale d'Orléans
Faculty of Sciences
Computer Science Department
University of Orléans
France

Past HLPP Workshops

• HLPP 2005 was held in Coventry (July 4-5, 2005). Parallel Processing Letters (volume 18, issue 1, 2008) containts revised papers presented at the workshop.
• HLPP 2003 was held in Paris (June 16-18, 2003). Parallel Processing Letters (Volume 13, issue 3) contains 14 revised papers presented at the workshop.
• HLPP 2001 was held in Orléans (March 26-27, 2001). Parallel Processing Letters (Volume 11,issue 4) contains 8 revised papers presented at the workshop. HLPP 2001 was a Studium workshop.